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| IA4320 Universal ISM Band he FSK Receiver S DESCRIPTION Integration's IA4320 is a single chip, low power, multi-channel FSK receiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 315, 433, 868, and 915 MHz bands. Used in conjunction with IA4220/21, Integration Associates' FSK transmitters, the IA4320 is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation. t4 e U . om c WIRELESS DATASHEET IA4320 PIN ASSIGNMENT FCS0 FBS0 FBS1 OUT0 OUT1 OUT2 OUT3 LPDM FCS3 FCS2 VDD IN1 IN2 VSS FCS1 XTL SDI SCK nSEL FFIT/SDO nIRQ DATA/nFFS DCLK/CFIL/FFIT CLK VDI ARSSI VDD IN1 IN2 VSS nRES XTL w w w .D ta a The IA4320 has a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency hopping, bypassing multipath fading, and interference to achieve robust wireless links. The PLL's high resolution allows the usage of multiple channels in any of the bands. The baseband bandwidth (BW) is programmable to accommodate various deviation, data rate, and crystal tolerance requirements. The receiver employs the Zero-IF approach with I/Q demodulation, therefore no external components (except crystal and decoupling) are needed in a typical application. The IA4320 is a complete analog RF and baseband receiver including a multi-band PLL synthesizer with an LNA, I/Q down converter mixers, baseband filters and amplifiers, and I/Q demodulator. The chip dramatically reduces the load on the microcontroller with integrated digital data processing: data filtering, clock recovery, data pattern recognition and integrated FIFO. The automatic frequency control (AFC) feature allows using a low accuracy (low cost) crystal. To minimize the system cost, the chip can provide a clock signal for the microcontroller, avoiding the need for two crystals. Standalone Mode For simple applications, the receiver supports a standalone operation mode. This allows complete data receiver operation and control of four digital outputs based on the incoming data pattern without a microcontroller. In this mode, 12 or more predefined frequency channels can be used in any of the four bands. For low power applications, the device supports low duty-cycle operation based on the internal wake-up timer. BLOCK DIAGRAM MIX I AMP IN1 13 LNA IN2 12 MIX Q PLL & I/Q VCO with cal. RF Parts w WTM with cal. AMP w OC LBD OC Self cal. w RSSI 15 .D COMP 1 2 3 t a AFC S a Data Filt CLK Rec FIFO e h 7 DCLK/ CFIL/ FFIT/ OUT2 DATA/ nFFS/ OUT2 t e * * * * * * * * * * * * * * * * * * * * * * * * * FEATURES clk I/Q Demod. data 6 DQD Fully integrated (low BOM, easy design-in) No alignment required in production Fast settling, programmable, high-resolution PLL Fast frequency hopping capability High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode) Direct differential antenna input Programmable baseband bandwidth (67 to 400 kHz) Analog and digital RSSI outputs Automatic frequency control (AFC) Data quality detection (DQD) Internal data filtering and clock recovery RX pattern recognition SPI compatible serial control interface Clock and reset signals for microcontroller 16 bit RX data FIFO Standalone operation mode without microcontroller Low power duty-cycle mode (less than 0.5 mA average supply current) Standard 10 MHz crystal reference Alternative OOK support Wake-up timer Low battery detector 2.2 to 5.4 V supply voltage Low power consumption (~9 mA in low bands) Low standby current (0.3 A) Compact 16-pin TSSOP package U 4 See back page for ordering information. .c m o Microcontroller Mode BB Amp/Filt./Limiter Data processing units TYPICAL APPLICATIONS * * * * * * * * * CLK div Xosc Controller Bias Low Power parts 8 CLK/ LPDM 9 XTL 4 5 nIRQ/ OUT1 16 VDI/ FCS3 10 nRES/ FCS1 11 14 ARSSI/ SDI/ FCS2 FCS0 SCK/ nSEL/ FFIT/ FBS0 FBS1 SDO/ OUT0 VSS VDD Remote control Home security and alarm Wireless keyboard/mouse and other PC peripherals Toy control Remote keyless entry Tire pressure monitoring Telemetry Personal/patient data logging Remote automatic meter reading IA4320-DS Rev 1.29r 1005 PRELIMINARY w w w .D at Sh a et e 4U . om c 1 www.integration.com IA4320 DETAILED DESCRIPTION General The IA4320 FSK receiver is the counterpart of the IA4220 FSK transmitter. It covers the unlicensed frequency bands at 315, 433, 868, and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL's high resolution allows for the use of multiple channels in any of the bands. The receiver employs the Zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application. The IA4320 consists of a fully integrated multi-band PLL synthesizer, an LNA with switchable gain, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator followed by a data filter. The RF VCO in the PLL performs automatic calibration, which requires only a few microseconds. Calibration always occurs when the synthesizer begins. If temperature or supply voltage changes significantly, VCO recalibration can be invoked easily. Recalibration can be initiated at any time by switching the synthesizer off and back on again. according to the characteristics of the signal to be received. An appropriate bandwidth can be selected to accommodate various FSK deviation, data rate, and crystal tolerance requirements. The filter structure is a 7-th order Butterworth low-pass with 40 dB suppression at 2*BW frequency. Offset cancellation is accomplished by using a high-pass filter with a cut-off frequency below 7 kHz. Data Filtering and Clock Recovery The output data filtering can be completed by an external capacitor or by using digital filtering according to the final application. Analog operation: The filter is an RC type low-pass filter and a Schmitt-trigger (St). The resistor (10k) and the St is integrated on the chip. An (external) capacitor can be chosen according to the actual bit-rate. In this mode the receiver can handle up to 256 kbps data rate. Digital operation: The data filter is a digital realization of an analog RC filter followed by a comparator with hysteresis. In this mode there is a clock recovery circuit (CR), which can provide synchronized clock to the data. With this clock the received data can fill the RX Data FIFO. The CR has three operation modes: fast, slow, and automatic. In slow mode, its noise immunity is very high, but it has slower settling time and requires more accurate data timing than in fast mode. In automatic mode the CR automatically changes between fast and slow modes. The CR starts in fast mode, then automatically switches to slow mode after locking. (Only the data filter and the clock recovery use the bit-rate clock. Therefore, in analog mode, there is no need for setting the correct bit-rate.) LNA The LNA has 250 Ohm input impedance, which works well with the recommended antennas. (See Application Notes available from www.integration.com.) If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide the correct matching and to minimize the noise figure of the receiver. The LNA gain (and linearity) can be selected (0, -6, -14, -20 dB relative to the highest gain) according to RF signal strength. This is useful in an environment with strong interferers. Data Validity Blocks RSSI A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on the filter capacitor used. Voltage on ARRSI pin vs. Input RF power Baseband Filters The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver P1 RSSI voltage [V] P3 P2 P4 Input Power [dBm] P1 P2 P3 P4 -65 dBm -65 dBm -100 dBm -100 dBm 1300 mV 1000 mV 600 mV 300 mV 2 IA4320 DQD The Data Quality Detector monitors the I/Q output of the baseband amplifier chain by counting the consecutive correct 0->1, 1->0 transitions. The DQD output indicates the quality of the signal to be demodulated. Using this method it is possible to "forecast" the probability of BER degradation. The programmable DQD parameter defines the threshold for signaling the good/bad data quality by the digital one-bit DQD output. In cases when the deviation is close to the bitrate, there should be four transitions during a single one bit period in the I/Q signals. As the bitrate decreases in comparison to the deviation, more and more transitions will happen during a bitperiod. signal which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The cause of the interrupt can be read out from the receiver by the microcontroller through the SDO pin. Interface and Controller An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock, wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the receiver and the received data. It is also possible to store the received data bits into the 16bit RX FIFO register and read them out in a buffered mode. FIFO mode can be enabled through the SPI compatible interface by setting the fe bit to 1 in the Output and FIFO Mode Command. AFC By using an integrated Automatic Frequency Control (AFC) feature, the receiver can synchronize its local oscillator to the received signal, allowing the use of: * inexpensive, low accuracy crystals * narrower receiver bandwidth (i.e. increased sensitivity) * higher data rate Crystal Oscillator The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet. The receiver can supply the clock signal for the microcontroller, so accurate timing is possible without the need for a second crystal. Standalone Operation Mode The chip also provides a standalone mode, which allows the use of the receiver without a microcontroller. This mode can be selected by connecting the CLK/LPDM pin to either VDD or VSS. After power on, the chip will check this pin. If it is connected to any supply voltage, then the chip will go to standalone mode. Otherwise, it will go to microcontroller mode and the pin will become an output and provide a clock signal for the microcontroller. To prevent the IA4320 from accidentally entering a standalone mode, the stray capacitance should be kept below 50 pF on pin 8. In this mode operating parameters can be selected from a limited set by "programming" the receiver over its pins. The chip is addressable and four digital output pins can be controlled by the received data. Selecting the Low Power Duty-Cycle Mode (LPDM) the chip consumes less than 0.5 mA average current. When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Configuration Setting Command, the chip provides a fixed number (128) of further clock pulses ("clock tail") for the microcontroller to let it go to idle or sleep mode. Low Battery Voltage Detector The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. Wake-Up Timer The wake-up timer has very low current consumption (1.5 A typical) and can be programmed from 1 ms to several days with an accuracy of 5%. It calibrates itself to the crystal oscillator at every startup, and then at every 30 seconds. When the crystal oscillator is switched off, the calibration circuit switches it back on only long enough for a quick calibration (a few milliseconds) to facilitate accurate wake-up timing. Event Handling In order to minimize current consumption, the receiver supports the sleep mode. Active mode can be initiated by several wake-up events (wake-up timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the serial interface). If any wake-up event occurs, the wake-up logic generates an interrupt 3 IA4320 PACKAGE PIN DEFINITIONS, MICROCONTROLLER MODE Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output Pin 1 2 3 SDI SCK nSEL FFIT/SDO nIRQ DATA/nFFS DCLK/CFIL/FFIT CLK VDI ARSSI VDD IN1 IN2 VSS nRES Name SDI SCK nSEL FFIT/SDO nIRQ DATA nFFS DCLK Type DI DI DI DO DO DO DI DO AIO Function Data input of serial control interface Clock input of serial control interface Chip select input of three-wire control interface (active low) FIFO IT (active low) or serial data out for Status Read Command. Tristate with bushold cell if nSEL=H Interrupt request output, (active low) Received data output (FIFO not used) FIFO select input Received data clock output (Digital filter used, FIFO not used) External data filter capacitor connection (Analog filter used) FIFO IT (active high) FIFO empty function can be achieved when FIFO IT level is set to one Clock output for the microcontroller Crystal connection (other terminal of crystal to VSS) / External reference input Reset output (active low) Negative supply voltage RF differential signal input RF differential signal input Positive supply voltage Analog RSSI output Valid Data Indicator output 4 5 6 7 CFIL FFIT XTL DO DO AIO DO S AI AI S AO DO 8 9 10 11 12 13 14 15 16 CLK XTL/REF nRES VSS IN2 IN1 VDD ARSSI VDI Typical Application, Microcontroller Mode Minimal Microcontroller Mode VCC Microcontroller Mode with FIFO Usage VCC VCC C1 1u C2 100p C3 10p C1 C1 1u 1u C2 C2 100p 100p C3 C3 10p 10p P3 P2 P1 P0 SDI SCK SDO nIRQ 1 2 3 4 5 6 7 8 16 15 14 13 IA4320 12 11 10 9 Antenna 250 Ohm nRESET CLKin VDI DRSSI P7 P7 SDI P6 SDI P6 SCK SCK P5 P5 nSEL P4 nSEL P4 SDO P3 SDO P3 nIRQ P2 nIRQ P2 nFFS nFFS P1 P1 FFIT P0 nFFE P0 Microcontroller Microcontroller nRESET CLKin nRESET CLKin 11 22 33 44 55 66 77 88 IA4320 IA4320 16 16 15 15 14 14 13 13 12 12 11 11 10 10 99 Microcontroller C4 C4 4.7n 4.7n Antenna Antenna 250 Ohm 250 Ohm X1 10MHz X1 X1 10MHz 10MHz 4 IA4320 PACKAGE PIN DEFINITIONS, STANDALONE MODE Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output Pin 1 2 FCS0 FBS0 FBS1 OUT0 OUT1 OUT2 OUT3 LPDM 1 2 3 4 5 6 7 8 16 15 14 FCS3 FCS2 VDD IN1 IN2 VSS FSC1 XTL Name FCS0 FBS0 FBS1 OUT0 OUT1 OUT2 OUT3 LPDM XTL FCS1 VSS IN2 IN1 VDD FCS2 FCS3 Type DI DI DI DO DO DO DO DI AIO DI S AI AI S DI DI Function Frequency select input bit0 Band select input bit0 Band select input bit1 Control output bit0 Control output bit1 Control output bit2 Control output bit3 Low power duty cycle mode select input Crystal connection (other terminal of crystal to VSS) or external reference input Frequency select input bit1 Negative supply voltage RF differential signal input RF differential signal input Positive supply voltage Frequency select input bit2 Frequency select input bit3 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IA4320 12 11 10 9 13 Typical Application, Standalone Mode VCC C1 1u C2 100p C3 10p GND * * * To LED, SSR, etc. load: 3mA max. OUT0 OUT1 OUT2 OUT3 1 2 3 4 5 6 7 8 16 15 14 * * Antenna 250 Ohm * IA4320 13 12 11 10 9 # X1 10MHz * Configuration pins: leave open or connect to VCC or GND # Configuration pin: connect to VCC or GND 5 IA4320 GENERAL DEVICE SPECIFICATION All voltages are referenced to Vss, the potential on the ground reference pin VSS. Absolute Maximum Ratings (non-operating) Symbol Vdd Vin Iin ESD Tst Tld Parameter Positive supply voltage Voltage on any pin Input current into any pin except VDD and VSS Electrostatic discharge with human body model Storage temperature Lead temperature (soldering, max 10 s) Min -0.5 -0.5 -25 -55 Max 6.0 Vdd+0.5 25 1000 125 260 Units V V mA V o o C C Recommended Operating Range Symbol Vdd Top Parameter Positive supply voltage Ambient operating temperature Min 2.2 -40 Max 5.4 85 Units V o C ELECTRICAL SPECIFICATION (Min/max values are valid over the whole recommended operating range, typ conditions: Top = 27 oC; Vdd = 2.7 V) DC Characteristics Symbol Idd Ipd Ilb Iwt Ix Vlb Vlba Vil Vih Iil Iih Vol Voh Parameter Supply current Standby current Low battery voltage detector current consumption Wake-up timer current consumption (Note 1) Idle current Low battery detect threshold Low battery detection accuracy Digital input low level Digital input high level Digital input current Digital input current Digital output low level Digital output high level Conditions/Notes 315 and 433 MHz bands 868 MHz band 915 MHz band All blocks disabled Min Typ 9 10.5 12 0.3 0.5 1.5 Max 11 12.5 14 Units mA A A A Crystal oscillator and baseband parts are ON Programmable in 0.1 V steps 2.2 3.0 3.5 5.3 mA V V mV 0.05 75 0.3*Vdd 0.7*Vdd Vil = 0 V Vih = Vdd, Vdd = 5.4 V Iol = 2 mA Ioh = -2 mA Vdd-0.4 -1 -1 1 1 0.4 V V A A V V Not Note 1: Using the internal wake-up timer and counter reduces the overall current consumption, which should permit approximately 6 months operation from a 1500mAh battery. 6 IA4320 AC Characteristics Symbol fLO Parameter Receiver frequency Conditions/Notes 315 MHz band, 2.5 kHz resolution 433 MHz band, 2.5 kHz resolution 868 MHz band, 5.0 kHz resolution 915 MHz band, 7.5 kHz resolution mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 With internal digital filters With analog filter BER 10-3, BW=67 kHz, BR=1.2 kbps (Note 1) fFSK: FSK deviation in the received signal In band interferers in high bands Out of band interferers f-fLO > 4MHz In band interferers in low bands Out of band interferers f-fLO > 4MHz BER=10-2 with continuous wave interferer in the channel BER=10-2 with continuous wave interferer in the adjacent channel, mode 0, channels at 134 kHz, BR=9.6 kbps, fFSK=30 kHz LNA: high gain LNA gain (0, -14 dB) LNA gain (-6, -20 dB) Min 310.24 430.24 860.48 900.72 60 120 180 240 300 360 Typ Max 319.75 439.75 879.51 929.27 75 150 225 300 375 450 115.2 256 Units MHz BW Receiver bandwidth 67 134 200 270 350 400 kHz BR BRA Pmin AFCrange IIP3inh IIP3outh IIP3inl IIP3outl CCR FSK bit rate FSK bit rate Receiver Sensitivity AFC locking range Input IP3 Input IP3 IIP3 (LNA -6 dB gain) IIP3 (LNA -6 dB gain) Co-channel rejection kbps kbps dBm -109 0.8*fFSK -21 -18 -15 -12 -7 -100 dBm dBm dBm dBm dB ACS Pmax Rin Cin RSa RSr CARSSI RSstep RSresp Adjacent channel selectivity Maximum input power RF input impedance real part (differential) (Note 2) RF input capacitance RSSI accuracy RSSI range Filter capacitance for ARSSI RSSI programmable level steps DRSSI response time 23 0 250 500 1 +/-5 46 1 6 dB dBm Ohm pF dB dB nF dB s Until the RSSI output goes high after the input signal exceeds the pre-programmed limit. CARRSI=5nF 500 Note 1: See the BER diagrams in the measurement results section for detailed information. Not Note 2: See matching circuit parameters and antenna design guide for information, and Application Notes available from http://www.integration.com. 7 IA4320 AC Characteristics (continued) Symbol fref fres tlock tst, P Cxl tPOR tsx tPBt twake-up Cin, D tr, f Parameter PLL reference frequency PLL frequency resolution PLL lock time PLL startup time Crystal load capacitance, see crystal selection guide Internal POR pulse width (Note4) Crystal oscillator startup time Wake-up timer clock period Programmable wake-up time Digital input capacitance Digital output rise/fall time 15 pF pure capacitive load Conditions/Notes (Note 3) Depends on selected bands Frequency error < 1kHz after 10 MHz step With running crystal oscillator Programmable in 0.5 pF steps, tolerance +/- 10% After Vdd has reached 90% of final value Crystal ESR < 100 Ohms Calibrated every 30 seconds 0.96 1 Min 8 2.5 Typ 10 20 250 8.5 50 16 100 5 1.08 5 * 10 2 10 11 Max 12 7.5 Units MHz kHz us us pF ms ms ms ms pF ns Note 3: Using other than a 10 MHz crystal is not recommended because the crystal referred timing and frequency parameters will change accordingly. Note 4: During this period, commands are not accepted by the chip. 8 IA4320 CONTROLINTERFACE Commands to the receiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent is an integer multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don't care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control registers. The receiver will generate an interrupt request (IRQ) for the microcontroller on the following events: * Supply voltage below the preprogrammed value is detected (LBD) * Wake-up timer timeout (WK-UP) * FIFO received the preprogrammed amount of bits (FFIT) * FIFO overflow (FFOV) FFIT and FFOV are applicable only when the FIFO is enabled. To find out why the nIRQ was issued, the status bits should be read out. Timing Specification Symbol tCH tCL tSS tSH tSHI tDS tDH tOD Parameter Clock high time Clock low time Select setup time (nSEL falling edge to SCK rising edge) Select hold time (SCK falling edge to nSEL rising edge) Select high time Data setup time (SDI transition to SCK rising edge) Data hold time (SCK rising edge to SDI transition) Data delay time Minimum Value [ns] 25 25 10 10 25 5 5 10 Timing Diagram tSS tSHI tCH SCK tDS SDI tDH tCL ~ ~ tOD ~ ~ nSEL tSH ~ ~ ~ ~ BIT 15 BIT 14 BIT 13 ~ ~ ~ ~ BIT 1 BIT 8 BIT 7 BIT 0 ~ ~ nIRQ POR ~ ~ W K-UP nIRQ 9 IA4320 Control Commands Control Word Configuration Setting Command Frequency Setting Command Receiver Setting Command Wake-up Timer Command Low Duty-Cycle Command Low Battery Detector and Clock Divider Command AFC Control Command Data Rate Command Data Filter Command Output and FIFO Command Related Parameters/Functions Frequency band, crystal oscillator load capacitance, baseband filter bandwidth, etc. Set the frequency of the local oscillator Set VDI source, LNA gain, RSSI threshold, Wake-up time period Enable low duty cycle mode. Set duty-cycle. Set LBD voltage and microcontroller clock division ratio Set AFC parameters Bit rate Set data filter type, clock recovery parameters Set FIFO IT level, FIFO start control, FIFO enable and FIFO fill enable Not Note : In the following tables the POR column shows the default values of the command registers after power-on. Configuration Setting Command bit 15 1 b1 0 0 1 1 b0 0 1 0 1 14 0 13 0 12 b1 11 b0 10 eb 9 et 8 ex 7 x3 6 x2 5 x1 4 x0 3 i2 2 i1 1 i0 0 dc POR 8936h 893Ah Frequency Band [MHz] 315 433 868 915 Baseband Bandwidth [kHz] reserved 400 340 270 200 134 67 reserved x3 0 0 0 0 1 1 x2 0 0 0 0 ...... 1 1 x1 0 0 1 1 1 1 x0 0 1 0 1 0 1 i2 0 0 0 0 1 1 1 1 i1 0 0 1 1 0 0 1 0 1 i0 0 1 0 1 0 1 0 1 Crystal Load Capacitance [pF] 8.5 9.0 9.5 10.0 .... 15.5 16.0 Bits eb eb and control the operation of of the low battery detector and wake-up Bits and et et control the operation the low battery detector and wake-up timer, respectively. They are enabled when the corresponding bit is set. timer, respectively. They are enabled when the corresponding bit is set. If is is the crystal is is active during sleep mode. If ex ex setset the crystal active during sleep mode. When dc bit is set it disables the clock output When dc bit is set it disables the clock output. 10 IA4320 Frequency Setting Command Bit bit 15 1 14 0 13 1 12 0 11 f11 10 f10 9 f9 8 f8 7 f7 6 f6 5 f5 4 f4 3 f3 2 f2 1 f1 0 f0 POR A680h The 12-bit Frequency Setting Command f0 = 10 MHz * C1 * (C2 + F/4000) The constants C1 and C2 are determined The constants C1 and C2 are determined byby the selected band as: the selected band as: Band [MHz] 315 433 868 915 C1 1 1 2 3 C2 31 43 43 30 Receiver Setting Command bit 15 1 14 1 13 0 12 0 11 0 10 0 9 0 8 0 7 d1 6 d0 5 g1 4 g0 3 r2 2 r1 1 r0 0 en er POR C0C1h Bits 7-6 select the VDI (valid data indicator) signal: Bits 7-6 select the VDI (valid data indicator) signal: d1 0 0 0 0 1 1 1 1 d0 0 0 1 1 0 0 1 1 output VDI output Digital RSSI Out (DRSSI) Digital RSSI Out (DRSSI) Quality Detector Output (DQD) Data Quality Detector Output (DQD) Clock recovery lock Clock recovery lock DRSSI && DQD Always Bits 5-4 LNA gain set: Bits 5-4 LNA gain set: g1 0 0 1 1 g0 0 1 0 1 GLNA (dB relative to max. G) 0 -14 -6 -20 Bits 3-1 control the threshold of the RSSI detector: Bits 3-1 control the threshold of the RSSI detector: r2 0 0 0 0 1 1 1 1 r1 0 0 1 1 0 0 1 0 r0 0 1 0 1 0 1 0 1 RSSIsetth [dBm] -103 -97 -91 -85 -79 -73 -67 -61 The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: RSSIth = RSSIsetth + GLNA Bit 0 (en) enables the whole receiver chain and crystal ocsillator when set. Enable/disable of the wake-up timer and the low battery detector are not affected by this setting. Note: Clock tail is not generated when the crystal oscillator is controlled by en bit. 11 IA4320 Wake-Up Timer Command bit 15 1 14 1 13 1 12 r4 11 r3 10 r2 9 r1 8 r0 7 m7 6 m6 5 m5 4 m4 3 m3 2 m2 1 m1 0 m0 POR E196h The wake-up time period can be calculated by M Low Duty-Cycle Command bit 15 1 14 1 13 0 12 0 11 1 10 1 9 0 8 0 7 d6 6 d5 5 d4 4 d3 3 d2 2 d1 1 d0 0 en POR CC08h CC0Eh With this command Low Duty-Cycle operation can be set in order to decrease the average power consumption. The time cycle is determined by the Wake-Up Timer Command. The Duty-Cycle is calculated by D Low Battery Detector and Microcontroller Clock Divider Command bit 15 1 14 1 13 0 12 0 11 0 10 0 9 1 8 0 7 d2 6 d1 5 d0 4 t4 3 t3 2 t2 1 t1 0 t0 POR C2E0h C200h The 5-bit value T of t4-t0 determines the threshold voltage of the threshold voltage Vlb of the detector: Vlb= 2.2 V + T * 0.1 V Clock divider configuration: d2 0 0 0 0 1 1 1 1 d1 0 0 1 1 0 0 1 1 d0 0 1 0 1 0 1 0 1 Clock Output Frequency [MHz] 1 1.25 1.66 2 2.5 3.33 5 10 12 IA4320 AFC Command Bit bit 15 1 14 1 13 0 12 0 11 0 10 1 9 1 8 0 7 a1 6 a0 5 rl1 4 rl0 3 st 2 fi 1 oe 0 en POR C665h C6F7h Bit 0 (en) enables the calculation of the offset frequency by the AFC circuit (it allows the addition of the content of the output register to the frequency control word of the PLL). Bit 1 (oe) when set, enables the output (frequency offset) register Bit 2 (fi) when set, switches the circuit to high accuracy (fine) mode. In this case the processing time is about four times longer, but the measurement uncertainty is less than half. Bit 3 (st) strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the output registers of the AFC block. Bit 4-5 (rl0, rl1) range limit: Limits the value of the frequency offset register to the following values: rl1 0 0 1 1 rl0 0 1 0 1 Max dev [fres] No restriction +15/-16 +7/-8 +3/-4 fres: 315, 433MHz bands: 2.5kHz 868MHz band: 5kHz 915MHz band: 7.5kHz Bit 6-7 (a0, a1) Automatic operation mode selector: a1 0 0 1 1 a0 0 1 0 1 Auto mode off (Strobe is controlled by microcontroller) Runs only once after each power-up Keep the foffset only during receiving (VDI=high) Keep the foffset value independently from the state of the VDI signal BASEBAND SIGNAL IN ATGL* ASAME* 10MHz CLK. /4 fi (bit2) en (bit0) VDI* au (bit6,7) Power-on reset (POR) rl1,0 (bit4,5) st (bit3) oe (bit1) F<11:0> from Frequency control word 0 1 M U X CLK DIGITAL LIMITER FINE 7 BIT 7 FREQ. OFFSET REGISTER OFFS <6:0> 12 BIT ADDER Fcorr<11:0> To synthesizer. DIGITAL AFC CORE LOGIC 7 ENABLE CALCULATION IF IN>MaxDEV THEN OUT=MaxDEV IF IN used in auto operation mode ELSE OUT=IN CLK CLR RANGE LIMIT STROBE OUTPUT ENABLE strobe output enable NOTE: *VDI (valid data indicator) is an internal signal of the controller. See the Receiver Setting Command for details. *ATGL: toggling in each measurement cycle *ASAME: logic high when the result is stable 13 IA4320 In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register), the AFC circuit is automatically enabled when VDI indicates a potential incoming signal during the whole measurement cycle and the circuit measures the same result in two subsequent cycles. There are three operation modes, example from the possible application: 1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, the extended TX/RX maximum distance can be achieved. Possible application: In the final application when the user is inserted the battery the circuit measures and compensate the frequency offset caused by the crystal tolerances. This method enables to use cheaper quartz in the application and provide quite good protection against locking in an interferer. 2a, (a1=1, a0=0) The circuit measures automatically the frequency offset during an initial low data rate pattern -easier to receive- (i.e.: 00110011) of the package and change the receiving frequency according that. The further part of the package can be received by the corrected frequency settings. 2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility to reduce it. In both cases (2a and 2b) when the VDI indicates poor receiving conditions (VDI goes low) the output register is automatically cleared. It's suggested to use when one receiver receives signal from more than one transmitter. 3, (a1=1, a0=1) It is similar to the 2a and 2b modes, but 3 issuggested to use when a receiver operates with only one transmitter. After a complete measuring cycle, the measured value is held independently of the sate of VDI signal. Data Filter Command bit 15 1 Bit 7 14 1 13 0 12 0 11 0 10 1 9 0 8 0 7 al 6 ml 5 1 4 s1 3 s0 2 f2 1 f1 0 f0 POR POR C42ChC42Ch Clock recovery (CR) auto lock control if set. It means that the CR start in fast mode after locking it automatically switches to slow mode. Clock recovery lock control 1: fast mode, fast attack and fast release 0: slow mode, slow attack and slow release Using the slower one requires more accurate bit timing (see Data Rate Command). Select the type of the data filter: s1 0 0 1 1 s0 0 1 0 1 Filter Type OOK to filter Digital Reserved Analog RC filter Bit 3-4 OOK to filter: the analog RSSI signal is used as received data. The DRSSI threshold level is used for slicing. Digital: this is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically adjusted to the bit rate defined by the Data Rate Command. Analog RC filter: the demodulator output is fed to the pin 7 over a 10 kOhm resistor. The filter characteristic is set by the external capacitor connected to this pin and VSS. (Suggested value for 9600 bps is 3.3 nF) Bit 0-2 Note: Note To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as well. 14 IA4320 Data Rate Command bit 15 1 14 1 13 0 12 0 11 1 10 0 9 0 8 0 7 cs 6 r6 5 r5 4 r4 3 r3 2 r2 1 r1 0 r0 POR C823h The expected bit rate of the received data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs. BR = 10 MHz / 29 / (R+1) / (1 + cs*7) In the receiver set R according the next function: R= (10 MHz / 29 /(1 + cs*7)/ BR) - 1 Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error. Data rate accuracy requirements: Clock recovery in slow mode: BR/BR<1/(29*Nbit) Clock recovery in fast mode: BR/BR<3/(29*Nbit) BR is the bit rate set in the receiver and BR is bit rate difference between the transmitter and the receiver. Nbit is the maximal number of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be careful to use the same division ratio in the receiver and in the transmitter. BR is a theoretical limit for the clock recovery circuit. Clock recovery will not work above this limit. The clock recovery circuit will always operate below this limit independently from process, temperature, or Vdd condition. E.g. Supposing a maximum length of consecutive zeros or ones in the data stream is less than 5 bits, the necessary relative accuracy is 0.68% in slow mode and 2.1% in fast mode. Output and FIFO Mode Command bit 15 1 14 1 13 0 12 0 11 1 10 1 9 1 8 0 7 f3 6 f2 5 F1 f1 4 f0 3 s1 2 s0 1 ff 0 fe POR POR CE89h CE85h Bit 4-7 FIFO IT level. The FIFO generates IT when number of the received data bits reaches this level. Set the input of the FIFO fill start condition: s1 0 0 1 1 s0 0 1 0 1 VDI Sycn. Word Reserved Always FIFO_WRITE_Logic (simplified) DATA (from data filter) CLK (from clock recovery) s0* s1* CR_LOCK DQD EN FIFO_WRITE _DATA FIFO_WRITE _CLK SEL0 SEL1 IN0 IN1 IN2 IN3 Q FIFO_WRITE _EN VDI Sync. Byte Detector Q SYNC BYTE SYNC BYTE && VDI LOGIC HIGH VDI nRES MUX fifo enable* fifo fill enable* nFIFO_RESET PIN 6 I/O port fifo enable* DIRECTION Note: * For details see the Output and FIFO mode Command 15 IA4320 Note: Note Bit 1: Status Read Command: The read command starts with a zero, whereas all other control commands start with a one. Therefore, after receiving the first bit of the control command the IA4320 identifies it as a read command. So as the first bit of the command is received, the receiver starts to clock out the status bits on the SDO output as follows: Status Register Read Sequence with FIFO Read Example nSEL 0 SCK instruction SDI interrupt bits out SDO FIFO IT FFOV* WK-UP* LBD* FFEM DRSSI DQD CRL ATGL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 status bits out ASAME OFFS<6> OFFS<4> OFFS<3> OFFS<2> OFFS<1> OFFS<0> (SGN) FIFO out FO FO+1 FO+2 FIFO IT NOTE: *Bits marked are internally latched. Others are only multiplexed out. It is possible to read out the content of the FIFO after the reading of the status bits. The command can be aborted after any read bits by rising edge of the select signal. Not Note : The FIFO IT bit behaves like a status bit, but generates nIRQ pulse if active. To check whether there is a sufficient amount of data in the FIFO, the SDO output can be tested. In extreme speed critical applications, it can be useful to read only the first four bits (FIFO IT - LBD) to FIFO clear the FFOV, WK-UP, and LBD bits. During the FIFO access the fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. If the FIFO is read in this mode the nFFS input must be connected to logic high level. Definitions of the bits in the above timing diagram: FIFO IT FFOV WK-UP LBD FFEM DRSSI DQD CRL ATGL ASAME OFFS6, 4-0 Number of the data bits in the FIFO is reached the preprogrammed limit FIFO overflow Wake-up timer overflow Low battery detect, the power supply voltage is below the preprogrammed limit FIFO is empty The strength of the incoming signal is above the preprogrammed limit Data Quality Detector detected a good quality signal Clock recovery lock Toggling in each AFC cycle AFC stablized (measured twice the same offset value) Offset value to be add to the value of the Frequency control word 16 IA4320 FIFO Buffered Data Read In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data Indicator (VDI) bit and/or the synchron word recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller. For further details see the Receiver Setting Command and the Output and FIFO Command. Polling Mode: The nFFS signal selects the buffer directly and its content could be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be taken. An SPI read command is also available. Interrupt Controlled Mode: The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case. FIFO Read Example with FFIT Polling: nSEL* 0 SCK 1 2 3 4 nFFS** FIFO read out SDO FIFO OUT FO+1 FO+2 FO+3 FO+4 FFIT NOTE: *nSEL is used to activate SDO **nFFS is used to select FIFO During FIFO access the fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. 17 IA4320 STANDALONE OPERATION The chip supports standalone operation, meaning that with preprogrammed (hard wired) parameters, a simple receiver can be built without an external microcontroller. After the power-up sequence, the status of pin 8 is queried by connecting internally about 10 uA current on it. If VSS or VDD is detected, the chip turns to standalone mode. In this case 7 pins are used to configure the receiver and 4 digital outputs are available: FCS 0 FB S 0 FB S 1 OUT0 OUT1 OUT2 OUT3 LPDM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FCS 3 FCS 2 V DD IN1 IN2 VSS FCS 1 XTL In the standalone mode, a predefined data sequence should be employed which contains preamble, synchron, chip address, and function control bytes. To allow the control of the outputs, the chip should receive its chip address byte and twice the same function control byte. The required data flow sequence: Chip Address Byte D4h AAh 2Dh D2h B4h B2h As a minimum preamble, use at least 16 bits. Preamble Byte Synchron Byte Function Control Byte Ones complement of Function Control Byte Function Control Byte See below See below See below The structure of the Function Control Byte is shown below: For each output there are two bits assigned to define their mode of operation: OUT3 F1 OUT3 F0 OUT2 F1 OUT2 F0 OUT1 F1 OUT1 F0 OUT0 F1 OUT0 F0 OUT3 / F1 sent out first. OUT0 - OUT3 represent the four digital output pins. F0 - F1 represents the function bits. Output functions controlled by the function bits, as follows: F1 0 0 1 1 F0 0 1 0 1 Function No change Sets output logical low Sets output logical high Sets output high in mono-stable mode, cycle time is 100 ms Mono-stable mode will be restarted as long as the proper Function Control Byte is received. 18 IA4320 The following receiving frequencies can be set with the different static external pin settings: Pin 16 FCS3 0 0 0 0 0 0 0 0 Z Z Z Z Z Z Z Z Pin 15 FCS2 0 0 0 0 Z Z Z Z 0 0 0 0 Z Z Z Z Pin 10 FCS1 0 0 Z Z 0 0 Z Z 0 0 Z Z 0 0 Z Z Pin 1 FCS0 0 Z or 1 0 Z or 1 0 Z or 1 0 Z or 1 0 Z or 1 0 Z or 1 0 Z or 1 0 Z or 1 Freceiving Pin 2=0 Pin 3=0 310.320 310.960 311.600 312.240 312.880 313.520 314.160 314.800 315.440 316.080 316.720 317.360 318.000 318.640 319.280 319.920 Freceiving Pin 2=1 Pin 3=0 433.360 433.440 433.520 433.600 433.680 433.760 433.840 433.920 434.000 434.080 434.160 434.240 434.320 434.400 434.480 434.560 Freceiving Pin 2=0 Pin 3=1 Freceiving Pin 2=1 Pin 3=1 Chip Address Byte D4h D2h B4h B2h D4h D2h B4h B2h D4h D2h B4h B2h D4h D2h B4h B2h (867.680) (867.840) (868.000) 868.160 868.320 868.480 868.640 868.800 868.960 869.120 869.280 869.440 869.600 869.760 869.920 (900.960) 902.880 904.800 906.720 908.640 910.560 912.480 914.400 916.320 918.240 920.160 922.080 924.000 925.920 927.840 (870.080) (929.760) Not 1: Note 1 Note 2 Not 2: Note 3 Not 3: Not 4: Note 4 Z: Not connected (floating) pin Values shown as (italic) are out-of-band frequencies. If FCS0=1 (connected to VDD) the RSSI threshold limit is changed from -103 dBm to -97 dBm. In standalone mode, the operation parameters related to the band, frequency selection, and chip address, are determined by the table above. All other control bits (filter bandwidth, bit rate etc.) are determined by the power-on values of the different control registers. 5: Note 5 It is possible to use the receiver in a so-called "mixed mode". The SPI bus architecture allows access to the bus in standalone mode (pins 1, 2, 3) and thereby makes it possible to overwrite the default POR values of the control registers. In this way the operating parameters of the receiver can be programmed over the interface while performing the functions of the standalone mode when receiving the proper data sequence. Low Power Duty-Cycle Operation (LPDM) To use this mode, pin 8 must be connected to VDD. The logic value of pin 8 defines whether the receiver works in Low Power Duty-Cycle Mode (LPDM) or not. If the value is high (VDD detected), the chip will wake up in every 300 ms. If the value is low (GND detected), then the chip is continually ON (active). The chip uses the internal wake-up timer and counter for timing the on/off process. This method reduces the overall current consumption, which should permit approximately 6 months operation from a 1500 mAh battery. 19 IA4320 Low Power Duty-Cycle Internal Operations and Timings The wake-up timer event switches on the crystal oscillator, the internal logic waits about 2.25ms. When the oscillator is stable the controller switches on the synthesizer as well. The receiver monitors the incoming signal strength during this "ON" state of LPDM. If in the next 6ms the incoming signal strength is above the defined limit (-103dBm if FCS0=0 or -97dBm if FCS0=1), the synthesizer remains switched on for 30.5ms, otherwise it switches itself off after the 6ms operation time. The period time is about 300ms. Xtal osc. enable Synthesizer enable 2.25ms 8.25ms 300ms 300ms 300ms 30.5ms 30.5ms DRSSI Pattern recognition Active Synchron word (2DD4h) received Start of new cycle 1: Note 1 Every detected synchron word restarts the timer which controls the `ON' state of the receiver. Not 2: Note 2 If the internal Pattern Recognition block is active (decoding the synchron word), then the internal logic doesn't switch the synthesizer off until the incoming data is fully processed. RX-TX ALIGNMENT PROCEDURES RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs. To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no offset if the CLK signals have identical frequencies. It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0). 20 IA4320 CRYSTAL SELECTION GUIDELINES The crystal oscillator of the IA4320 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used. When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup. The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO). Therefore fLO is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error. Maximum XTAL Tolerances Including Temperature and Aging [ppm] Bit Rate: 2.4kbps 30 315 MHz 433 MHz 868 MHz 915 MHz 30 20 10 10 60 75 50 25 25 Transmitter Deviation [+/- kHz] 90 100 75 40 40 120 100 100 60 50 150 100 100 75 75 180 100 100 100 75 210 100 100 100 100 Bit Rate: 9.6kbps 30 315 MHz 433 MHz 868 MHz 915 MHz 25 15 8 8 60 70 50 25 25 Transmitter Deviation [+/- kHz] 90 100 75 40 40 120 100 100 60 50 150 100 100 75 70 180 100 100 75 75 210 100 100 100 100 Bit Rate: 38.3kbps 30 315 MHz 433 MHz 868 MHz 915 MHz don't use don't use don't use don't use 60 30 20 10 10 Transmitter Deviation [+/- kHz] 90 75 50 30 25 120 100 75 40 40 150 100 100 60 60 180 100 100 75 75 210 100 100 100 75 Whenever a low frequency error is essential for the application, it is possible to "pull" the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the "midrange", for example 16 pF. The "pull-ability" of the crystal is defined by its motional capacitance and C0. The on chip AFC is capable to correct TX/RX carrier offsets as much as 80% of the deviation of the received FSK modulated signal. Note: There may be other requirements for the TX carrier accuracy with regards to the requirements as defined by standards and/or channel separations. 21 IA4320 MEASUREMENTRESULTS Measurement Setup A group of decoupling capacitors is placed to provide very low supply noise for the measurements. R1-C1 forms a low pass filter to block the CLK signal going down to the test-board on pin 2 of the connector. Layout and Assembly Drawing for the 50 Test-Board to LNA 50ohm C1 L1 AC LNA 250ohm to LNA C1 Top Layer Matching Circuit Frequency [MHz] 915 868 433 315 L1 [nH] 15 15 36 56 C1 [pF] 3 3 7 9 Bottom Layer Circuit Parameters 22 IA4320 BER Measurement Results BER in the 433 MHz Band 1.E+00 1.E-01 1.E-02 1.1kbps 2.4kbps 4.8kbps 9.6kbps 19.2kbps 1.E-04 38.4kbps 1.E-05 1.E-06 -115 57.6kbps 115kbps -110 -105 Input Pow er [dBm] -100 -95 BER 1.E-03 BER inat 915MHz Band BER the 915 MHz Band 1.E+00 1.1kbps 2.4kbps 1.E-02 4.8kbps 9.6kbps 19.2kbps 1.E-04 1.E-05 38.4kbps 57.6kbps 115kbps 1.E-06 -110 -105 -100 Input Pow e r [dBm] -95 -90 1.E-01 BER 1.E-03 1.134 kbps BW=67 kHz fFSK =30 kHz 2.4 kbps BW=67 kHz 4.8 kbps BW=67 kHz 9.6 kbps BW=67 kHz 19.2 kbps BW=67 kHz 38.4 kbps 57.6 kbps 115 kbps fFSK =30 kHz fFSK =30 kHz fFSK =45 kHz fFSK =45 kHz fFSK =90 kHz BW=134 kHz BW=134 kHz BW=200 kHz fFSK =90 kHz fFSK =120 kHz The table shows the optimal BW and fFSK selection for different data rates 23 IA4320 Frequency Offset Effected Sensitivity Degradation Sensitivity versus offset at BER=1e-3 Sensitivity Versus Offset at BER=1e-3 -80 no AFC -85 AFC Sensitivity [dBm] -90 -95 -100 -105 0 10 20 30 Offse t [kHz] BR=9.6 kbps, BER=10-3 , BW=67 kHz, fFSK =60 kHz 40 50 60 Sensitivity Versus Offset atat BER=1e-3 Sensitivity versus offset BER=1e-3 -80 -85 Sensitivity [dBm] -90 -95 -100 -105 0 10 20 30 Offset [kHz] 40 50 60 BR=9.6 kbps, BER=10-3 , BW=134 kHz, fFSK =60 kHz 24 IA4320 Input impedance Measured input return loss on the demo boards with suggested matching circuit 315 MHz Matching to 50 Ohm R315 matching to 50 Ohm magdB(S11) 0 -5 -10 -15 R315 matching to 50 Ohm 433 MHz Matching to 50 Ohm magdB(S11) magdB(S11) 0 -5 0 -5 -10 -10 -15 -20 -15 -25 -30 -20 -25 -30 -35 -40 200 220 240 260 280 300 freq. [MHz] 320 340 360 380 400 S11 [dB] S11 [dB] S11 [dB] -20 -25 -35 -40 300 320 340 360 380 200 220 240 260 280 -30 300 400 420 320 440 340 460 360 480 380 500 400 freq. [MHz] freq. [MHz] 868 and 915 MHz Matching to 50 Ohm RHB matching to 50 Ohm magdB(S11) 0 50ohm Input matching Circuit Input Matching circuit to LNA C1 L1 -5 AC LNA 250ohm -10 -15 to LNA S11 [dB] -20 -25 -30 -35 -40 800 C1 820 840 860 880 900 920 940 960 980 1000 freq. [MHz] freq [MHz] Frequency [MHz] 915 915 868 868 433 433 315 315 L [nH] L1 [nH] 15 15 15 15 36 36 56 56 C1 [pF] C1 [pF] 3 3 3 3 7 7 9 9 25 IA4320 TYPICAL APPLICATIONS Wireless Keyboard Demo Receiver (915 MHz) Schematic PCB Layout of Wireless Keyboard Demo Receiver (operating in the 915 MHz band) Top Layer Bottom Layer 26 IA4320 Push-Button Demo Receiver (434 MHz) Schematics PCB Layout of Push-Button Receiver Demo Circuit (operating in the 434 MHz band) Top Layer Bottom Layer 27 IA4320 PACKAGEINFORMATION 16-pin TSSOP 28 IA4320 ORDERING INFORMATION IA4320 Universal ISM Band FSK Receiver DESCRIPTION IA4320 16-pin TSSOP die ORDERING NUMBER IA4320-IC CC16 Revision # see Integration Associates Demo Boards and Development Kits DESCRIPTION Development Kit Wireless Keyboard Demo RF Link Analysis Board Remote Temp. Monitoring Station ORDERING NUMBER IA ISM - DK IA ISM - DA WK IA ISM - DA RF Link IA ISM - DA TempDemo Related Resources DESCRIPTION Antenna Selection Guide Antenna Development Guide IA4220 Universal ISM Band FSK Transmitter ORDERING NUMBER IA ISM - AN1 IA ISM - AN2 see http://www.integration.com for details Note: Volume orders must include chip revision to be accepted. Integration Associates, Inc. 110 Pioneer Way, Unit L Mountain View, California 94041 Tel: 650.969.4100 Fax: 650.969.4582 www.integration.com info@integration.com techsupport@integration.com P480 This document may contain preliminary information and is subject to change by Integration Associates, Inc. without notice. Integration Associates assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Integration Associates or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. (c)2004, Integration Associates, Inc. All rights reserved. Integration Associates and EZRadio are trademarks of Integration Associates, Inc. All other trademarks belong to their respective owners. 29 |
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